1. Field of the Invention
Embodiments of the invention relate to operational amplifier circuits that maintain a constant gain over a wide range of common mode input voltages.
2. Description of the Related Art
With the recent trends of a unipolar driving power supply and decreased power supply voltage Vdd, operational amplifier circuits of a rail-to-rail input type are drawing attention in which an input voltage range is expanded over nearly power supply voltage width of GND to Vdd. For instance, a differential input circuit, which is a MOS differential pair composed of MOS-FETs, is connected in parallel with a cascode amplification circuit to enhance a gain. A technology is further known that holds the trans-conductance gm of the MOS differential pair constant to reduce higher harmonic distortion of the output signal.
FIG. 4 shows an example of schematic construction of a conventional operational amplifier circuit of a rail-to-rail input folded cascode type. The operational amplifier circuit of FIG. 4 includes a P-MOS differential pair A for differentially amplifying an common mode input voltage given to a pair of voltage input terminals INP and INM, and an N-MOS differential pair B provided in parallel with the P-MOS differential pair A. The P-MOS differential pair A is composed of a pair of MOS-FETs of a P channel type (hereinafter referred to simply as a P-MOS) 1a and 1b, and the N-MOS differential pair B is composed of a pair of MOS-FETs of an N channel type (hereinafter referred to simply as an N-MOS) 2a and 2b 
A grounded-gate type P-MOS 3, which is connected in series to the sources of the pair of MOS-FETs 1a and 1b composing the P-MOS differential pair A, composes a P-MOS current source C for the P-MOS differential pair A. A grounded-gate type N-MOS 4, which is connected in series to the sources of the pair of MOS-FETs 2a and 2b composing the N-MOS differential pair B, composes an N-MOS current source D for the N-MOS differential pair B.
A cascode circuit of an input folded type for the P-MOS differential pair A and the N-MOS differential pair B is composed of an N-MOS cascode amplification stage E and a P-MOS cascode amplification stage F. The N-MOS cascode amplification stage E consists of an N-MOS 5a, the source of which is connected to the drain of the P-MOS 1a, and an N-MOS 5b, the source of which is connected to the drain of the P-MOS 1b. The P-MOS cascode amplification stage F consists of a pair of P-MOS 6a and P-MOS 6b that are cascode-connected to the respective drains of the N-MOS 5a and the N-MOS 5b. A pair of P-MOS 7a and P-MOS 7b forming a current mirror circuit are connected to the sources of the P-MOS 6a and the P-MOS 6b and work as a load on the P-MOS cascode amplification stage F. This pair of P-MOSes 7a and 7b is a P-MOS active load G acting on the P-MOS differential pair A. A pair of N-MOS 8a and N-MOS 8b forming a current mirror circuit are connected to the sources of the N-MOS 5a and the N-MOS 5b and work as a load on the N-MOS cascode amplification stage E. This pair of N-MOSes 8a and 8b is an N-MOS active load H acting on the N-MOS differential pair B.
The P-MOS active load G acting on the P-MOS differential pair A works also as a current source for the N-MOS differential pair B; and the N-MOS active load H acting on the N-MOS differential pair B works also as a current source for the P-MOS differential pair A. In short, the P-MOSes 7a and 7b work simultaneously as a P-MOS active load G on the P-MOS differential pair A and as a current source for the N-MOS differential pair B; and the N-MOSes 8a and 8b work simultaneously as an N-MOS active load H on the N-MOS differential pair B and as a current source for the P-MOS differential pair A.
The current as indicated in FIG. 4 flows through the P-MOS differential pair A and the N-MSO differential pair B when the common mode input voltages given to the voltage input terminals INP and INM are equal to each other and the voltages are not approximately equal to the ground potential GND, zero volts, and not near the power supply voltage Vdd. The current I3 flows through the P-MOS current source C composed of the P-MOS 3; the current I4 flows through the N-MOS current source D composed of the N-MOS 4; and the current I7 flows through the P-MOS active load G composed of the P-MOSes 7a and 7b. 
In the operational amplifier circuit provided with the P-MOS differential pair A and the N-MOS differential pair B connected together in parallel, either one of the P-MOS differential pair A and the N-MOS differential pair B operates normally in the input voltage range of the ground potential GND to the power supply voltage Vdd. Since an input voltage can be amplified in an input voltage range of approximately the power supply voltage width, from GND to Vdd, the operational amplifier circuit is called a rail-to-rail input type operational amplifier circuit.
The cascode circuit is composed of the N-MOS cascode amplification stage E and the P-MOS cascode amplification stage F and forms a grounded-gate amplifier circuit. The cascode circuit amplifies by folding the current flowing through the P-MOS differential pair A and the N-MOS differential pair B raising the output resistance and enhances the gain of the operational amplifier circuit. Kenji TANIGUCHI: “Introduction to CMOS Analogue Circuits for LSI Design” (in Japanese) First edition, published by CQ Publishing Co. Ltd., December 2004, pages 200-204 (also referred to herein as “Non-patent Document 1”) discloses in detail about an operational amplifier circuit of a rail-to-rail input folded cascode type.
In the operational amplifier having a construction described above, when the common mode input voltage is approximately equal to the power supply voltage Vdd, the N-MOS differential pair B solely operates; and the common mode input voltage is approximately equal to the ground potential GND zero volts, the P-MOS differential pair A solely operates. In these cases, different from the case in which the common mode input voltage is in an ordinary state and both the P-MOS deferential pair A and the N-MOS differential pair are operating, the bias conditions have been changed for the P-MOS differential pair A and the N-MOS differential pair B, resulting in variation of the gain of the operational amplifier circuit.
A gain ‘Gain’ of the operational amplifier circuit having the construction described above is represented by the following equations:Gain=(g mp+g mn)/(X+Y),X=(g d6/g m6)(g dn+g d7), andY=(g d5/g m5)(g dp+g d8).
In these equations, g mp is a trans-conductance of the P-MOS differential pair A and g dp is a drain conductance of the P-MOS differential pair A; and g mn is a trans-conductance of the N-MOS differential pair B and g dn is a drain conductance of the N-MOS differential pair B. g m6 and g d6 are a trans-conductance and a drain conductance, respectively, of the P-MOS 6a of the P-MOS cascode amplification stage F; and g m5 and g d5 are trans-conductance and the drain conductance, respectively, of the N-MOS 5a of the N-MOS cascode amplification stage E. g d7 is a drain conductance of the P-MOSes 7a and 7b of the active load G for the P-MOS differential pair, and g d8 is a drain conductance of the N-MOSes 8a and 8b of the active load H for the N-MOS differential pair.
When the common mode input voltage is low to turning the N-MOS differential pair B OFF, the trans-conductance g mn and the drain conductance g do of the N-MOS differential pair B becomes zero, resulting in decrease in the numerator term in the above equation. Here, the current drawn out by the N-MOS differential pair B decreases, increasing the bias current through the active loads G and H. As a result, the drain conductances g d7 and g d8 increases, lowering the gains of the cascode circuits E and F, which increases the denominator term of the above equation resulting in lowering the Gain of the operational amplifier circuit.
To deal with this problem, a measure as shown in FIG. 5 has been proposed in which constant trans-conductance circuits J and K are provided for the P-MOS differential pair A and the N-MOS differential pair B, respectively. The constant trans-conductance circuit J is a P-MOS differential pair compensating circuit to maintain the trans-conductance g mp of the differential pair A and the constant trans-conductance circuit K is an N-MOS differential pair compensating circuit to maintain the trans-conductance g mn of the differential pair B. When one of the P-MOS differential pair A and the N-MOS differential pair B has turned OFF, the constant trans-conductance circuits J and K supply twice the current in an normal state to the differential pair that stays in an ON state, avoiding decrease in the Gain. This measure is disclosed in Non-Patent Document 1, for example.
The constant trans-conductance circuit J for P-MOS differential pair compensation is composed of a pair of P-MOSes 9a and 9b that form a current mirror circuit and delivers a current to the P-MOS differential pair A and an N-MOS 9c that regulates a current through the current mirror circuit corresponding to the current in the N-MOS differential pair B. The ratio of the currents in the constant trans-conductance circuit J is set at [I4: 3 I3]. The constant trans-conductance circuit K for N-MOS differential pair compensation is composed of a pair of N-MOSes 10a and 10b that form a current mirror circuit and draws a current from the N-MOS differential pair B and an P-MOS 10c that regulates a current through the current mirror circuit corresponding to the current in the P-MOS differential pair A. The ratio of the currents in the constant trans-conductance circuit K is set at [I3: 3 I4].
As shown in FIG. 5, which indicates the current flow in the state of the P-MOS differential pair A OFF, the constant trans-conductance circuit K for compensating the N-MOS differential pair operates to deliver the four times as much as the current in a normal state to the N-MOS differential pair B when the P-MOS differential pair A turns OFF. Similarly, the constant trans-conductance circuit J for compensating the P-MOS differential pair operates to deliver the four times as much as the current in a normal state to the P-MOS differential pair A when the N-MOS differential pair B turns OFF. Here, because the trans-conductances g m of the P-MOS differential pair A and the N-MOS differential pair B are each proportional to the square root of the current in the P-MOS differential pair A and the N-MOS differential pair B, respectively, the trans-conductances gm each becomes twice when the current becomes four times.
The constant trans-conductance circuit J for compensating the P-MOS differential pair and the constant trans-conductance circuit K for compensating the N-MOS differential pair operating as described above hold the magnitude of the numerator term of the above equation irrespective of the variation of the common mode input voltage. Therefore, the Gain of the operational amplifier circuit is held constant.
In the operational amplifier circuit of a rail-to-rail input folded cascode type having the constant trans-conductance circuits J and K, however, when one of the MOS differential pairs A and B is in an OFF state, the other MOS differential pair needs to carry four times as much current as the current in the normal state. As a result, the active loads G and H must carry at least four times current of the current through the P-MOS differential pair A and through the N-MOS differential pair B. This detracts from freedom of circuit design and hinders reduction of power consumption.
The operational amplifier circuit having the construction as described above is theoretically possible to make the numerator term of the equation mentioned previously constant to maintain a constant gain. However, the variation of the current flowing through the active loads G and H and through the cascode amplification stages E and F changes the apparent drain conductances g d of the P-MOSes 6a and 7a and N-MOSes 5a and 8a composing the active loads G and H and the cascode amplification stages E and F. Consequently, the denominator term of the equation changes and eventually changes the gain of the operational amplifier circuit.